Physical Design Engineer

Requirements

• Experience working in high-performance ASIC design environments
• Strong fundamentals in digital logic, circuit design, and process technology
• Familiarity with DFT concepts and testing methodologies
• Strong scripting and automation skills (Python, Tcl, shell), including parsing and analyzing tool outputs
• Ability to design robust methodologies, diagnose complex failures, and improve physical design flows
• Applied use of statistics in analyzing timing, power, or design data (preferred)
• Hands-on experience with static timing analysis and timing closure methodologies
• Expertise using industry-standard physical design and signoff tools (e.g., Innovus, PrimeTime)

About the role

Responsibilities

• Drive design-for-test (DFT) methodologies and implementation
• Contribute to physical implementation, from RTL handoff through GDSII on advanced process nodes
• Partner on floorplanning and physical optimization for high-performance, latency-critical designs
• Close timing across multiple modes and corners while optimizing power, performance, and area (PPA)
• Diagnose and resolve physical design issues such as timing bottlenecks, congestion, and IR/EM violations
• Build, maintain, and improve repeatable, automated physical design flows
• Develop scripts and tooling to improve productivity, robustness, and insight into design behavior
• Collaborate closely with RTL, architecture, and other hardware engineers to influence design decisions early

What you'll get

• $200k–$300k base salary
• medical
• dental
• vision
• basic life insurance
• enrollment in our company’s retirement savings plans
• sick and parental leave
• other paid time off (including 20 vacation days and 10 paid holidays in the US)

Skills

Python · Tcl · shell · static timing analysis · timing closure · Innovus · PrimeTime · design-for-test (DFT) · floorplanning · IR/EM analysis · digital logic · circuit design