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ASIC Engineer

Jane Street
🇺🇸New YorkSeniorFull-timePosted October 29, 2025

About the Role

Design, test and deploy advanced hardware designs as part of the Ultra Low Latency team. Collaborate with colleagues across trading, networking and research infrastructure. Contribute to FPGA-based and ASIC-based technology projects, leveraging innovative hardware development tools like Hardcaml to improve productivity and reliability in the hardware engineering process.

Requirements

  • 4+ years of practical experience in RTL design and verification, with a significant focus on ASIC design verification
  • Experience verifying ASIC designs using either Synopsys or Cadence tools
  • Experience applying software engineering techniques to improve the hardware design process and programming in high-level languages such as Python, C++, Java, or Haskell
  • Additional (preferred) experience in any of the following: formal verification, front-end RTL design and synthesis, or back-end physical design
  • Happy to work on both FPGA-based and ASIC-based technologies
  • Excited about the advantages that better tools can bring, and willing to try new things as a result