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ASIC Engineer

Jane Street
🇬🇧LondonSeniorFull-timePosted October 29, 2025

About the Role

We are looking to hire an experienced ASIC Engineer to help us design, test and deploy advanced hardware designs. As part of our Ultra Low Latency team, you'll collaborate with people across trading, networking and research infrastructure. You'll contribute to projects using both FPGA-based and ASIC-based technologies.

We believe tools improve the productivity and reliability of hardware engineering. We created Hardcaml, a hardware development toolchain embedded in OCaml. We're looking for hardware engineers excited about better tools and willing to try new approaches.

Requirements

  • 4+ years of practical experience in RTL design and verification, with a significant focus on ASIC design verification
  • Experience verifying ASIC designs using either Synopsys or Cadence tools
  • Experience applying software engineering techniques to improve the hardware design process and programming in high-level languages such as Python, C++, Java, or Haskell
  • Additional (preferred) experience in any of the following; formal verification, front-end RTL design and synthesis, or back-end physical design
  • Fluent in English
  • Happy to work on both FPGA-based and ASIC-based technologies