ASIC Physical Design Engineer
Jane StreetAbout the Role
We are looking to hire an ASIC Physical Design Engineer to help design, test and deploy advanced hardware as part of our Ultra Low Latency team. You'll collaborate with people across the firm including trading, networking and research infrastructure. This is not a traditional PD role—you'll be expected to lead with physical design expertise while thinking like a chip designer, owning PD flows end-to-end, and being comfortable reading and writing RTL to reason about cross-boundary design decisions. We're looking for hardware engineers who have worked across the stack, whether transitioning from RTL design to PD or having worn multiple hats on smaller teams, and who are excited about using better tools like our Hardcaml hardware development toolchain to improve the hardware design process.
Requirements
- 8+ years hands-on experience building and running modern physical design flows (e.g., floorplanning, place and route, timing closure, physical verification, power analysis)
- Broad enough experience across PD to own a flow end-to-end and know where the risks are
- Can read and write RTL and understand how front-end design decisions affect physical implementation—and vice versa
- Thinks about physical design in the context of the overall chip, not just as a downstream consumer of a netlist
- Interested in using software engineering techniques to improve the hardware design process
- Experience programming in a high-level language (Python, C++, Haskell, etc.)
- Fluent in English