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ASIC Physical Design Engineer

Jane Street
🇺🇸New YorkSeniorFull-timePosted April 30, 2026

About the Role

We are looking to hire an ASIC Physical Design Engineer to help design, test, and deploy advanced hardware. As part of the Ultra Low Latency team, you'll collaborate across the firm with people in trading, networking, and research infrastructure. This role requires physical design expertise combined with chip design thinking—you'll own a PD flow end-to-end while being able to read and write RTL and reason about design decisions crossing the front-end/back-end boundary.

Requirements

  • 8+ years hands-on experience building and running modern physical design flows (e.g., floor planning, place and route, timing closure, physical verification, power analysis)
  • Broad enough experience across PD to own a flow end-to-end and know where the risks are
  • Can read and write RTL and understand how front-end design decisions affect physical implementation—and vice versa
  • Thinks about physical design in the context of the overall chip, not just as a downstream consumer of a netlist
  • Interested in using software engineering techniques to improve the hardware design process
  • Experience programming in a high-level language (Python, C++, Haskell, etc.)
  • Experience owning a PD flow end-to-end
  • Experience reading and writing RTL
  • Comfortable reasoning about design decisions that cross the front-end/back-end boundary
  • Worked across the stack, either started as an RTL designer and moved into PD, or was on a smaller team wearing multiple hats
  • Excited about the advantages that better tools can bring, and willing to try new things as a result