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Hardware Engineer (FPGA/ASIC)

Jane Street
🇬🇧LondonStudentFull-timePosted August 3, 2026

About the Role

Join Jane Street as a summer intern on the hardware team, working on both FPGA and ASIC designs using Hardcaml, an OCaml library for hardware description in RTL. You'll be paired with full-time mentors who'll guide you on real-world projects, learning how programming language technology can improve hardware design, testing, and validation. Over the internship, you'll build hardware applications from concept to working design, collaborating closely with experienced engineers and gaining exposure to Jane Street's shared tech stack and development environment.

Requirements

  • Comfortable with a software programming language
  • Experienced with a Hardware Description (or Construction) language (VHDL, Verilog, Chisel, Pymtl, or other), for both writing and testing hardware designs
  • Experienced working with FPGA or ASIC vendor tools - Vivado or Quartus for FPGAs, Genus or Innovus for ASICs
  • Experienced with building a working hardware project (either FPGA or ASIC) through an academic, professional, or personal project
  • Interested in learning how to use FPGAs or ASICs in the context of networking
  • Fluent in English
  • No previous knowledge of Hardcaml is required