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2027 Internship - FPGA Engineer

Virtu Financial
🇮🇪DublinStudentInternPosted August 12, 2026

About the Role

At Virtu, this internship places you at the center of ultra-low latency trading, where you will tackle actual engineering challenges that keep trading systems competitive. You will work with experienced engineers on the full FPGA and ASIC design lifecycle—from architecture and RTL implementation through simulation, verification, and bring-up on live hardware. This 10-week programme (21 June - 27 August 2027) includes ongoing training, real problems to solve, mentorship from senior engineers, and a company-curated global training week. No finance background is required; what matters most is how you think and how you learn.

Requirements

  • Academic background in Electrical or Computer Engineering
  • Experienced with Hardware Description Languages (SystemVerilog, Verilog)
  • Experience working with FPGA vendor tools — Vivado or Quartus for FPGAs
  • Comfortable with Software programming languages (Python, C++, or similar)
  • Interested in learning how FPGAs and ASICs are used in the context of low latency trading systems
  • Strong problem solving and communication skills
  • Graduating year of 2028

What You'll Get

  • Daily catered lunches, fully stocked kitchen, on-site gym & workout classes, games room, social events and laundry service
  • Company-curated global training week for interns
  • Ongoing training throughout the summer
  • Several senior mentors throughout the programme
  • Engaging social events